PLX08 Project - Knight Rider Car: Difference between revisions
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When the next CLOCK pulse arrives, The SERIAL INPUT and the D-input of the second D-type are both at logic 1. Output A remains at 1 and output B becomes 1. Each new pulse tranfsers the logic 1 signal to the next stage of the shift register. You can follow these changes in logic levels from the V/t graphs given in the next diagram: | When the next CLOCK pulse arrives, The SERIAL INPUT and the D-input of the second D-type are both at logic 1. Output A remains at 1 and output B becomes 1. Each new pulse tranfsers the logic 1 signal to the next stage of the shift register. You can follow these changes in logic levels from the V/t graphs given in the next diagram: | ||
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Revision as of 12:42, 10 March 2008
Knight Rider
This Project was created by Frazer Fyfe, Mark McGowan, Christine Orr and Lynn Wiseman
Concept
For our project we decided to replicate the light sequence from Kit, The Knight Rider car. The lights flash in a linear sequence from left to right, and then back again.
At the centre of this circuit is a CD4015 Dual 4-bit Shift Register
A shift register consists of a chain of bistables connected together so that data can be transferred along the chain from one end to the other.
In this circuit the Clock inputs of all D-Types are connected. This is a key feature of the circuit of a shift register.
On the first rising edge, also called a LOW to HIGH transition, the logic state at the SERIAL INPUT is transferred to A, the output of the first D-type. This happens after a short delay, known as the propagation delay of the D-type. Before this change, the logic state at the D-input of the second D-type was LOW, logic 0. This 0 is transferred to B. In other words, no change in logic state is observed.
When the next CLOCK pulse arrives, The SERIAL INPUT and the D-input of the second D-type are both at logic 1. Output A remains at 1 and output B becomes 1. Each new pulse tranfsers the logic 1 signal to the next stage of the shift register. You can follow these changes in logic levels from the V/t graphs given in the next diagram:
The connection from NOT-Q back to the SERIAL INPUT of the shift register prevents the shift register from getting stuck in any particular state. The outputs follow a definite sequence. With four D-types, there are 2x4=8 different output states:
Ring counters show the action of shift registers clearly. The sequence produced has 2n different states, where n is the number of D-types. The 4017 decade counter contains a 5-stage ring counter with its outputs decoded to provide 10 individual outputs.
